The ride-sharing firm's new processor handles sensor fusion & neural network inference with ultra-low latency onboard.
At a Glance
- Waymo's new 5nm ASIC delivers 1,000 TOPS to process lidar, radar and camera data in real time.
- The custom chip reduces temporal noise in low-light conditions to enhance object perception.
- Dual redundant compute systems ensure seamless failover if one unit experiences a fault during operation.
Autonomous ride-sharing company Waymo has found that delivering the compute power necessary to deliver fully autonomous vehicles that deliver passengers to destinations with no human intervention requires compute power demanded a new purpose-built 5nm application-specific integrated circuit (ASIC).
Writing for the company’s blog, Satish Jeyachandran, Vice President of Engineering, and Daniel Rosenband, Compute Lead, introduced Waymo’s latest processing hardware, which is designed to process the avalanche of incoming raw data before it reaches the ride-share car’s core machine learning compute system.
They describe this new chip as a “specialized machine learning powerhouse engineered exclusively to process, fuse, and run advanced neural networks on raw sensor data in real time.”
That sounds impressive, as does the 1,000 TOPS ASIC system's ability to extract critical information from the raw lidar, radar, and camera data streams. The company specifically calls out the chip’s ability to reduce the temporal noise in low-light images to improve the perception of objects.
Waymo’s purpose-built 5nm ASIC. WAYMO
The authors describe a trio of hardware requirements they say are non-negotiable:
Responsive: To make real-time driving decisions, the autonomous system operates entirely onboard, constantly processing decisions within milliseconds. We have engineered our stack for ultra-low latency, minimizing the delay from first pixel to action.
Ruggedized: The hardware operates under constant vibration, shock, and extreme temperatures.
Redundant: While they normally operate as one unit running full parallel workloads, if one compute system experiences a fault, the other seamlessly takes over.
Waymo had advanced its own in-house silicon’s compute power by a factor of 20x in eight years, and taps into its cars’ liquid cooling system to keep those chips in their operating temperature range year-round. The compute system packs beneath the vehicle’s trunk floor, preserving cargo space for passengers.
By co-designing custom silicon with the sensor and algorithms, Waymo achieves unmatched efficiency and performance. The latest system (right) processes high-fidelity data from 13 high-resolution cameras simultaneously and in real time, delivering exceptional low-light perception and revealing critical environmental details that traditional cameras (left) miss. WAYMO
The blog authors explain that the company built a machine learning-primary architecture to run advanced neural networks at minimal latency. Then they plug in the best CPUs, GPUs, and accelerators to manage critical non-ML tasks like orchestration, data movement, and logging.
While this new ASIC is in-house silicon, Waymo stresses its continuing partnerships with suppliers such as AMD, Micron, NVIDIA, Samsung, Sandisk, Socionext, and TSMC in its mission to develop the most capable autonomous computing system.
Facts Only
Waymo developed a custom 5nm application-specific integrated circuit (ASIC).
The processor delivers 1,000 TOPS of performance.
The chip processes data from lidar, radar, and 13 high-resolution cameras.
The hardware is designed to reduce temporal noise in low-light images.
The system utilizes dual redundant compute units for failover.
The chips are integrated with the vehicle's liquid cooling system.
Hardware is positioned beneath the vehicle's trunk floor.
The architecture prioritizes machine learning, supplemented by CPUs, GPUs, and accelerators.
Waymo maintains partnerships with AMD, Micron, NVIDIA, Samsung, Sandisk, Socionext, and TSMC.
In-house silicon compute power increased 20x over eight years.
Executive Summary
Waymo has introduced a purpose-built 5nm ASIC designed to handle the massive data throughput required for fully autonomous ride-sharing. Delivering 1,000 TOPS, the processor focuses on real-time sensor fusion and neural network inference, specifically targeting the reduction of temporal noise in low-light conditions to improve object perception. The system is engineered for ultra-low latency, ruggedization against environmental stress, and redundancy to ensure operational safety in the event of a hardware fault.
To maintain these performance levels, the hardware is housed beneath the trunk floor and integrated into the vehicle's liquid cooling system. While the core architecture is a custom machine learning powerhouse, it operates alongside standard CPUs and GPUs for orchestration and logging. This internal development is conducted in parallel with ongoing partnerships with major semiconductor firms, including NVIDIA, TSMC, and Samsung, to optimize the overall autonomous computing stack.
Full Take
The strongest version of this narrative is that vertical integration—designing the silicon in tandem with the sensors and algorithms—is the only way to achieve the latency and reliability required for Level 4/5 autonomy. By removing the "middleman" of general-purpose hardware, Waymo claims a leap in efficiency and perception.
However, because this information originates from company leadership via a corporate blog, it functions as a strategic signal to investors and competitors. The emphasis on "non-negotiable" requirements and "unmatched efficiency" utilizes a common industry pattern: presenting engineering milestones as insurmountable moats. By citing a 20x increase in power over eight years, the narrative frames Waymo not just as a software company, but as a hardware powerhouse, shifting the perceived value of the company toward its proprietary IP.
Patterns detected: ARC-0061 Authority Game
The underlying paradigm is technological determinism—the belief that more compute (TOPS) and smaller nodes (5nm) directly equate to safer driving. This ignores the "long tail" of edge cases where raw processing power cannot substitute for nuanced semantic understanding of human behavior. The second-order consequence is an intensifying "compute arms race" in autonomous transit, where safety is measured by hardware benchmarks rather than transparent, third-party validation of failure rates.
If this were a coordinated influence campaign, the playbook would involve "technobabble" (using terms like TOPS and ASIC) to create a veneer of scientific inevitability, discouraging critics from questioning the actual safety record by overwhelming them with hardware specifications. The current content aligns partially with this, as it focuses heavily on the "how" of the chip rather than the "how often" of system disengagements.
Bridge Questions:
1. Does an increase in TOPS linearly correlate with a decrease in accident rates, or is there a point of diminishing returns?
2. How does the reliance on custom, proprietary silicon affect the ability of external regulators to audit the decision-making process of the vehicle?
3. What are the energy costs and environmental impacts of deploying 1,000 TOPS of liquid-cooled compute in every vehicle of a mass-market fleet?
Counterstrike Scan: The content matches the structural pattern of a corporate capability announcement; it is designed to project dominance through technical specifications rather than to invite scientific scrutiny.