About twenty years ago I worked with Cliff Hou, LC Lu, and the TSMC PDK team on reference flows with emerging EDA and IP companies. This was the precursor to the OIP. Having a person with LC Lu’s depth of R&D experience running the TSMC Design & Technology Platform is truly an honor, absolutely.
AI is creating two related problems for semiconductor designers. They must deliver more computing power for training and inference, while keeping energy use and cost manageable. Dr. LC Lu’s presentation at the TSMC Open Innovation Platform Forum describes a response built around more efficient transistors, closer integration of logic and memory, larger multi-chip packages, optical connections, and AI-assisted chip design.
The central challenge is useful work per unit of energy. An AI system’s cost is shaped not only by how quickly its processors calculate, but also by how much power they draw and how efficiently they receive data. Training a model requires immense computation. Serving that model to users adds a different burden: every generated token consumes processing, memory access and communication capacity. As inference use grows, small improvements in energy per token can have large effects across a data center.
The first part of TSMC’s approach is continued process improvement. New semiconductor processes can improve power, performance and area, the three measures commonly shortened to PPA. The presentation discusses nanosheet transistors and design technology co-optimization, in which engineers adapt circuit design and manufacturing technology together. A transistor alone does not determine a chip’s efficiency. Standard-cell layouts, wiring, placement and the demands of a particular workload all affect the result. TSMC has described its NanoFlex family as giving designers choices that help balance performance and energy efficiency.
Those choices matter because AI hardware is not uniform. A component designed for maximum speed may justify a different circuit layout from one designed for lower power or smaller area. Even within a single system, designers may use different kinds of cells where speed is critical and where it is less important. This is a practical limit on any simple claim that a newer manufacturing process will automatically make every AI workload cheaper: designers still have to turn the process’s capabilities into a working product.
The second part of the roadmap moves beyond the individual chip. AI processors need to exchange enormous amounts of data with high-bandwidth memory, or HBM. If computation becomes faster while memory access does not, processors can spend time waiting for data. Placing memory close to compute through advanced packaging increases the bandwidth available between them and can reduce the energy needed to move each bit. The presentation discusses a hierarchy of memory technologies rather than one universal replacement, reflecting different trade-offs in capacity, bandwidth, latency and power.
Advanced packaging also lets designers combine multiple computing dies in one system. TSMC’s CoWoS technology is an example of this approach, while its 3DFabric portfolio includes three-dimensional stacking. The attraction is scale: engineers can bring together more logic and memory than would fit comfortably on one conventional die. The difficulty is that package size, electrical connections, heat removal, power delivery, testing and manufacturing yield all become system-level design problems. TSMC’s 2026 forum materials place 3DFabric and advanced packaging alongside its leading-edge processes as essential parts of future AI design.
As systems grow, communication between them becomes another constraint. The presentation points to TSMC-COUPE, its compact optical engine, as a path toward high-bandwidth, energy-efficient networking. Optical links use light to carry information and may help where electrical links become costly in power or difficult to scale over distance. This does not mean every wire inside a chip disappears. It means designers are looking for the right connection at each level—from circuitry within a die to communication between large AI systems. TSMC lists co-packaged optics among the technologies featured at its 2026 forum.
The presentation’s other major theme is design productivity. More elaborate processes and packages create more decisions for engineers and more conditions their designs must satisfy. Electronic design automation, or EDA, tools already help turn a circuit plan into a physical layout and check whether it can be manufactured. The presentation describes a proposed AI-oriented design enablement kit and agent-based workflows that could help optimize placement and routing, identify and fix design-rule violations, migrate existing designs, and translate descriptions of three-dimensional chip architectures into a standard design format.
These are consequential tasks, but automation must be judged by the quality of the finished design, not only by how quickly a tool produces an answer. A proposed change still has to meet electrical, thermal, timing and manufacturing requirements. An AI agent may generate options and run repeated tool flows around the clock; engineers and verified design tools must establish that the result works. TSMC describes autonomous AI workflows with its ecosystem partners as a focus of the 2026 forum, while its established Open Innovation Platform brings together design tools, intellectual property and manufacturing guidance.
Shared design descriptions matter in this setting. LC Lu discusses 3Dblox as a way to describe complex multi-die architectures so that different tools and organizations can work from consistent information. TSMC previously introduced 3Dblox for three-dimensional chip design, with the goal of improving interoperability among design tools. For a package assembled from several dies, that common representation can reduce the risk that teams make incompatible assumptions about connections or physical arrangement.
Bottom line: AI progress increasingly depends on improving a whole computing system, not merely making one processor faster. Memory bandwidth, package integration, networking, energy supply and the time needed to design and validate a product can each become the limiting factor. TSMC’s presentation describes these constraints as connected engineering problems: improve the silicon, bring components closer together, move data more efficiently and help designers manage the resulting complexity.
Also Read:
The Intelligence Revolution: TSMC’s OIP Ecosystem Forges the Path to Trillion-Transistor AI Systems
Podcast EP368: An Overview of TSMC Open Innovation Platform (OIP) event with Aveek Sarkar
Comparison of TSMC CoWoS-S, CoWoS-R, and CoWoS-L
TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win Orders
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Facts Only
* Twenty years ago, the author worked with Cliff Hou, LC Lu, and the TSMC PDK team on reference flows with emerging EDA and IP companies, which preceded the OIP.
* AI creates two related problems for semiconductor designers: delivering more computing power while managing energy use and cost.
* Dr. LC Lu presented a response at the TSMC Open Innovation Platform Forum describing solutions involving more efficient transistors, logic/memory integration, larger packages, optical connections, and AI-assisted chip design.
* The central challenge is useful work per unit of energy.
* Process improvement involves nanosheet transistors and design technology co-optimization.
* Standard-cell layouts, wiring, placement, and workload affect efficiency, noting that newer processes do not automatically make all AI workloads cheaper for designers to realize a working product.
* Memory placement closer to compute via advanced packaging increases bandwidth and reduces energy per bit moved.
* TSMC’s CoWoS technology and 3DFabric portfolio enable combining multiple dies in one system.
* Communication constraints are addressed by technologies like TSMC-COUPE, the compact optical engine.
* A proposed AI-oriented design enablement kit and agent-based workflows aim to automate placement, routing, and design rule checking.
* Shared design descriptions, such as 3Dblox, aim to ensure interoperability across different tools for complex multi-die architectures.
Executive Summary
The evolution of semiconductor design is being shaped by the dual challenges posed by Artificial Intelligence: increasing computational demands and the necessity for energy efficiency. Dr. LC Lu's work addresses this through innovations like more efficient transistors, closer integration of logic and memory, advanced packaging techniques, optical connections, and AI-assisted chip design. The central objective across these advancements is maximizing useful work per unit of energy, as the cost of AI systems depends on computation speed, power draw, and data efficiency.
One approach involves continued process improvement, focusing on nanosheet transistors and design technology co-optimization to balance performance and energy efficiency based on specific workload demands. Another direction focuses on system-level integration, leveraging advanced packaging like CoWoS and 3DFabric to place memory closer to compute and enable higher bandwidth. Further constraints involve communication, addressed through technologies like optical links, and the need for improved design productivity via AI-oriented workflows that automate complex tasks while maintaining rigorous validation against electrical and thermal requirements. Ultimately, progress depends on solving interconnected engineering problems across the entire computing system.
Full Take
The narrative frames the AI hardware challenge not merely as a speed problem but as a systemic constraint defined by the entire computing stack—from silicon physics to system-level packaging and software workflows. The implicit assumption is that process scaling alone is insufficient; real optimization requires holistic architectural choices made by designers regarding trade-offs in power, latency, and physical arrangement.
The tension arises between incremental material science gains (better transistors) and macro-architectural restructuring (3D integration, optical networking). This suggests a pattern where technical progress must be mediated by workflow changes. The move towards AI-assisted design enablement hints at a shift from tool automation to autonomous decision-making, raising critical questions about the locus of responsibility when errors occur in complex, multi-agent workflows.
The concept of shared design descriptions, like 3Dblox, points toward a structural necessity for interoperability; if disparate teams are optimizing parts of an AI system, inconsistency becomes an unmanageable source of error and inefficiency. The connection between physical reality (heat, power delivery) and abstract representation (design descriptions) suggests that the final bottleneck will be in the translation layer, where embodied physics must map cleanly onto digital intent. Where does this necessity for holistic management fit within the competitive pressures of specialized component design? What frameworks are needed to govern the integration of process-level optimization with system-level packaging strategies when dealing with increasingly autonomous AI workflows?
Sentinel — Human
The text functions as an expert analysis synthesizing specific technical strategies from a forum to frame the systemic challenges of AI hardware development, demonstrating high contextual understanding.