SAN JOSE, Calif. — AI chip startup Etched has raised $300 million in a Series C round at a $10 billion pre-money valuation, bringing the total raised to $1.1 billion. Etched’s round was led by Sequoia with participation from A16Z, Jane Street, Blackstone, SK Hynix, Diffusion Capital, plus existing investors.
The company already has $1 billion in pre-orders, Etched president Robert Wachen told EE Times on a recent visit to the company’s San Jose headquarters.
“In general, we are focused on the biggest AI companies and the biggest AI clusters in the world,” Wachen said. “Our customers are buying many billions of dollars of hardware… we expect that the product will be very good for coding, long context, long horizon agents, and a lot of things that inference tokens are going to be used for.”
Customers are already running their workloads remotely in Etched’s data center with results that are “significantly better than anything on the market”, Wachen said.
In addition to the cluster and lab up and running in the company’s San Jose office, Etched recently opened a new R&D facility in Milpitas, Calif., which includes a 10 MW data center plus a lab and quick turn SMT line.
Workload flexibility
Etched, started by Harvard dropouts Gavin Uberti and Chris Zhu with Harvard graduate Robert Wachen, attracted attention two years ago when it said it could beat Nvidia Blackwell-based systems’ token throughput by an order of magnitude using chips that “burned the transformer architecture into hardware”. Today, the technical story has evolved a bit, Wachen said, but the company’s aims are just as ambitious.
“Early on, we tried a bunch of different ideas, some very radical, like hard-coding a specific model or a specific model architecture into hardware,” he said. “What we realized is that the world needs a new computing paradigm that enables more FLOPS and bandwidth, that can run any type of inference workload, whether that’s multi-trillion parameter MoE models, or diffusion, or state-space models.”
More flexibility on workloads is part of Etched’s technical evolution, along with a broader focus on system and cluster-level topologies, in keeping with industry trends, Wachen said.
EE Times visited the Etched office in San Jose for a tour of the lab and an impressive large MoE inference demo, and was able to see racks of hardware up and running in prefill and decode configurations. Etched declined to make performance figures public at this stage, however.
Vertical integration
The company is vertically integrated, since its ambitious design has meant taking on parts of the stack other fabless startups usually wouldn’t. Every part of Etched’s rack, from the ASIC design to custom packaging, board design and cooling to server and infrastructure design, was done in-house, Wachen said.
“We’re deep believers in vertical integration,” he said. “It’s not enough to build a chip, it’s not enough to build the server, it’s not enough to build the rack, it’s not even enough to build a cluster. You have to build a machine that can produce the best clusters in the world at gigawatt scale.”
Etched is both dogmatic and pragmatic about its vertically integrated approach, Wachen said. The overall aim is simply to do what it takes to serve more tokens than the competition. It’s a big ask for a startup, but the team is over 450 and growing.
Low-voltage inference
A big part of Etched’s performance comes from utilization, which indirectly comes from turning down the voltage for parts of its chips. Today’s big AI chips suffer from thermal issues, which means cores have to be throttled (clock frequency reduced to reduce heat loss), with a resulting loss in performance.
Etched is running the transistors in its math engines at “under half” the voltage other AI chips use in a scheme it calls low-voltage inference (LVI). This enables more FLOPS per Watt, and it also means better utilization of those FLOPS, Wachen said, since throttling isn’t required. The company can run at 80%+ utilization for trillion-parameter MoE models without thermal throttling.
“The current state of affairs is that for every FLOPS I buy, I’m really getting 0.2 to 0.4 FLOPS,” he said. “If every chip in the world ran LVI, we could double or triple the world’s inference capacity.”
There is a reason sub-threshold designs are generally limited to small chips (such as Ambiq’s microcontrollers) and crypto-mining ASICs. Running at low voltage means extremely high current, with resulting challenges in handling current spikes, and in general the clock frequencies that can be achieved are very slow.
“This is an extremely hard physical problem,” Wachen said. “There’s tons of innovations across the stack from things at the fabrication level, things at the ASIC design, packaging, board, cooling and mechanical levels. Everything has to go together to make this happen.”
Will Etched have to reduce its clock frequency significantly to make it all work?
“Not necessarily,” Wachen said. “Of course, it’s hard to run a high clock speed at low voltage, mainly because the current goes up, but there are ways to solve these problems. One of the breakthroughs is how to run at much lower voltages than GPUs or other AI chips while being able to run a much larger amount of silicon.”
Part of the solution is running only the math engines at lower voltage; the chip’s SRAM blocks can’t (sub-threshold operation isn’t possible today for standard SRAM cells as it reduces the stability too much). For this reason, competitors’ designs that finely mix compute and SRAM would find low-voltage operation harder, Wachen said.
“These are hard problems to be solved, but our hardware is the proof we’ve found a solution,” he said.
Etched’s chip is on TSMC N4P, and it’s a full-reticle-sized design with six stacks of HBM. Wachen said the chip deliberately uses a different process node, different packaging technology, and different memory than Nvidia’s next-generation Rubin GPUs to enable both to get to scale simultaneously.
Cluster-scale memory
Another of Etched’s key innovations is a low-latency shared memory pool across a whole cluster in a single scale-up domain using a custom high-bandwidth interconnect for fast access to both SRAM and HBM across chips.
“That meant both a new type of interconnect and a new type of memory subsystem had to be co-designed throughout the stack to make it possible,” Wachen said. “And we need to do that with technologies that exist and are mass-producible today, including copper.”
In Etched’s lab, the company has split prefill and decode stages across separate racks of Etched chips, and can easily handle both because of their compute and bandwidth, Wachen said. That said, Etched would be just as happy to be deployed alongside other hardware in a disaggregated setup, he added.
Etched racks will start shipping to customers this summer.
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Facts Only
* Etched raised $300 million in a Series C round at a $10 billion pre-money valuation.
* The total amount raised by the company is $1.1 billion.
* Customers are running workloads remotely in Etched’s data center, reporting results "significantly better than anything on the market."
* Etched has $1 billion in pre-orders.
* The company was founded by Gavin Uberti and Chris Zhu, with Robert Wachen.
* Etched aims to improve performance for coding, long context, and long horizon agents, as well as inference tokens.
* Etched operates a new R&D facility in Milpitas, California, which includes a 10 MW data center, a lab, and a quick turn SMT line.
* The company vertically integrates the stack, handling ASIC design, packaging, board design, cooling, and infrastructure internally.
* Low-voltage inference (LVI) runs math engines at under half the voltage of other AI chips, enabling better FLOPS per Watt by avoiding thermal throttling.
* Etched's chip is on TSMC N4P and features six stacks of HBM.
* The company implemented a low-latency shared memory pool across a cluster using a custom high-bandwidth interconnect.
Executive Summary
Etched recently secured $300 million in a Series C funding round, valuing the company at a $10 billion pre-money valuation, bringing its total raised to $1.1 billion. The funding was led by Sequoia, with participation from A16Z, Jane Street, Blackstone, SK Hynix, and Diffusion Capital. The company has secured $1 billion in pre-orders for its hardware. Etched focuses on creating AI chips that can handle large context and long horizon agents, targeting the largest AI companies and clusters globally.
The company’s technical work centers on a novel approach to compute, aiming to surpass current systems by utilizing the transformer architecture directly in hardware. This involved exploring radical ideas like hard-coding model architectures into silicon before evolving to a focus on achieving greater FLOPS and bandwidth for various inference workloads, such as multi-trillion parameter MoE models and diffusion models.
A core innovation is low-voltage inference (LVI), where transistors operate at under half the voltage used by other AI chips, which enhances performance per watt by minimizing thermal throttling. The company has pursued vertical integration, handling everything from ASIC design and packaging to server infrastructure in-house. Furthermore, they have developed a cluster-scale memory pool using a custom interconnect for fast access across the entire system.
Full Take
The narrative surrounding Etched demonstrates a strategic pivot from incremental chip design to creating a complete, vertically integrated system capable of addressing fundamental physical and architectural limitations in AI hardware. The central tension lies between the ambition of achieving groundbreaking performance through low-voltage computation (LVI) and the immense difficulty of solving the associated physical constraints—managing high current spikes while maintaining stability across complex stacked systems.
The pursuit of vertical integration is not merely an engineering choice but a philosophical stance: the belief that system performance requires control over the entire stack, from silicon design to infrastructure topology. This suggests an underlying pattern where success in next-generation AI hardware may depend less on incremental improvements in one layer and more on holistic, physics-aware co-design across all layers simultaneously.
The LVI strategy reveals a fundamental re-framing of performance: rather than pushing clock speeds against thermal limits (the traditional approach), the focus shifts to maximizing utilization through energy efficiency. The current state—where every FLOPS purchased yields only 0.2 to 0.4 actual FLOPS—suggests that the market is currently suffering from significant inefficiency imposed by thermal constraints, which are being tackled via hardware-level innovation rather than just algorithmic refinement.
The real implication for cognitive sovereignty lies in recognizing that technological leaps often require addressing unstated physical barriers. The success of Etched hinges on solving these "extremely hard physical problems" across the entire stack, suggesting that true competitive advantage resides in holistic system design over isolated component optimization. What assumptions about current industry practices regarding thermal management and memory hierarchy might be holding back broader adoption of such LVI paradigms?
Sentinel — Human
The article reads like standard, specialized tech journalism, providing factual details while allowing for expert opinion to frame complex technological advancements.