Taiwan Semiconductor Manufacturing Company (TSMC)’s decision to upgrade its second facility in Japan’s Kumamoto to a 3-nanometer (nm) process marks a broader transition in the geography of advanced semiconductor manufacturing: from a commercially driven concentration model to a security-oriented distribution of capacity among allies. This move not only strengthens Japan’s position in the Indo-Pacific semiconductor sector, but also shows that chip competition is increasingly being shaped by geopolitics rather than market logic.
According to Taiwan’s Department of Investment Review, TSMC has revised the investment plan for its Japan Advanced Semiconductor Manufacturing (JASM) project in Japan to adopt a 3nm process, with a planned monthly capacity of 15,000 12-inch wafers. Equipment installation and mass production are expected to begin in 2028. At the commercial level, this can be seen as a response to market demand and customer needs. Strategically, it shows that Japan is seeking to embed more advanced manufacturing capabilities into its domestic industrial security framework.
Over the past decades, Japan’s semiconductor policy has consistently revolved around the idea of “restoring capability”: reinforcing its strengths in materials and equipment, supporting the public-private joint venture Rapidus, and attracting TSMC and other international firms to invest locally in order to reduce vulnerability to external supply chain shocks.
Japan’s chip strategy report also suggests that Tokyo’s logic is not simply one of industrial revitalization, but of redefining semiconductors as part of a broader de-risking and technology security agenda. This means that TMSC’s Kumamoto fab is not merely a local investment project. Instead, it has become an important adjustment in the geostrategic configuration of the Indo-Pacific semiconductor landscape.
TSMC is distributing more advanced production capacity across Japan, the United States, and its homebase in Taiwan, which reflects the strategic diffusion of advanced manufacturing capability among security partners. For Japan, this enhances its status within an alliance-based supply chain. For Taiwan, it shifts its so-called “silicon shield” toward a more distributed layout characterized by a trusted partner network. Such an adjustment serves both industrial resilience and political signaling.
Currently, the advanced semiconductor industry remains highly dependent on cross-border specialization. No single country can monopolize the entire supply chain. Therefore, chip competition is not about who can achieve complete self-sufficiency, but about who can secure sufficient access and maintain trusted cooperative networks in times of crisis.
Japan is using state subsidies, strategic partnerships, and industrial investment attraction to embed itself more deeply within the core security circle of advanced semiconductors. For Tokyo, the most important significance of the second Kumamoto facility’s upgrade to 3nm is that this process is working.
JASM is led by TSMC, with shareholding participation from Sony, Denso, and Toyota, and the total investment has already exceeded $20 billion. In 2024, the Japanese government approved subsidies of up to $4.62 billion for JASM’s second facility. The facility had originally been planned to produce 6nm to 12nm chips, but has now been approved for 3nm production.
At the same time, the upgrade reflects Japan’s broader policy ambitions in advanced computing, artificial intelligence, the defense industry, and high-end manufacturing. Japanese Prime Minister Takaichi Sanae has linked advanced chip capabilities to economic security and national competitiveness, and indicated that Japan will continue to provide policy support for upgrading its semiconductor industry. Therefore, the process upgrade at the second Kumamoto facility can be viewed as part of Japan’s broader national strategy to proactively shape industrial outcomes.
TSMC’s Kumamoto 3nm upgrade reveals a deeper transformation in Indo-Pacific tech geopolitics: chip competition is not merely a race for corporate efficiency, but is increasingly becoming a process through which states reorganize advanced manufacturing capacity through trusted partner networks. This indicates that chip competition is shifting from a model of globalized division of labor and toward a security-driven redistribution based on networks of trust.