What you’ll learn:
- How to split the load for facial recognition.
- Some of Microchip’s processors that can handle smart-home chores.
In the video above, Microchip’s Brad Poole, Edge AI Business Development Manager, and Bill Li, Applications Manager for Microprocessors, highlight the SAM9x75 and SAMA7D65 application processors in a simulated smart-home environment. In this case, the SAM9x75 handles the image capture and optimization with its image sensor controller (ISC). The image is then passed via Ethernet to the SAMA7D65 that runs the facial recognition stack (Fig. 1).
The SAM9x75 is based on an Arm ARM926 core. It incorporates 64K SRAM and a DDR2/3L interface. However, for this application, it’s the MIPI 4-lane CSI-2 camera interface and the built-in image sensor controller (ISC) that are important. The ISC supports ITU-R BT 601/656/1120 video interface up to 5 Mpixels as well as raw Bayer 12, YCbCr, monochrome and JPEG compressed sensors up to 12 bits. This provides a smart camera via Ethernet that improves the image quality before passing it on.
The SAMA7D65 is an Arm Cortex-A7 application processor running Linux. It gets the video stream via its 100/1000 Ethernet MAC with time-sensitive networking (TSN) support. The chip is supported by the Microchip Graphics Suite and MPLAB Machine Learning Development Suite. The chip is where the facial recognition software runs.
The application was running on the SAMA7D65 Curiosity Kit (Fig. 2). The board has a microSD slot plus 8 Gb of DDR3L, 64 Mb of QSPI NOR flash, 4 Gb of SLC NAND flash and a 2-kb serial EEPROM.
The SAMA7D65 Curiosity Kit provides two Ethernet ports (Fig. 3). One via a conventional RJ-45 jack and the other via the SODIMM socket. There are three on-board CAN-FD transceivers, too.
Also in the mix are a 40-pin Raspberry Pi expansion header, a pair of mikroBUS connectors, and a pair of PIOBU/system headers. The security support starts with a physically unclonable function (PUF) and includes secure boot, secure key storage, and high-performance crypto accelerators for AES, SHA, RSA, and ECC.
About the Author
William G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
I still get a hand on software and electronic hardware. Some of this can be found on our Kit Close-Up video series. You can also see me on many of our TechXchange Talk videos. I am interested in a range of projects from robotics to artificial intelligence.
Brad Poole
Edge AI Business Development Manager, Microchip Technology
Brad Poole is Edge AI Business Development Manager at Microchip Technology. He holds a Master's degree in international business from Saint Louis University.
Bill Li
Applications Manager for Microprocessors, Microchip Technology
Bill Li is Applications Manager for Microprocessors at Microchip Technology. He holds a Bachelor of Applied Science from Queen's University and Master of Business Administration from The University of Arizona Global Campus.
Facts Only
* The SAM9x75 handles image capture and optimization with an ISC.
* The SAMA7D65 runs the facial recognition stack.
* The SAM9x75 is based on an Arm ARM926 core with 64K SRAM and a DDR2/3L interface.
* The ISC supports ITU-R BT 601/656/1120 video interfaces up to 5 Mpixels and 12-bit sensors.
* The image is passed from the SAM9x75 via Ethernet to the SAMA7D65.
* The SAMA7D65 runs facial recognition software.
* The SAMA7D65 has a 100/1000 Ethernet MAC with TSN support.
* The Curiosity Kit features two Ethernet ports and CAN-FD transceivers.
* Security features include a Physically Unclonable Function (PUF), secure boot, key storage, and crypto accelerators.
* The SAMA7D65 Curiosity Kit includes 8 Gb of DDR3L memory and various flash storage.
Executive Summary
Facial recognition in a smart home environment is demonstrated using Microchip processors in a simulated setting. The system involves two main components: the SAM9x75, which handles image capture and optimization via an image sensor controller (ISC), and the SAMA7D65, which runs the facial recognition software. The SAM9x75 is based on an Arm ARM926 core and features a MIPI 4-lane CSI-2 camera interface with an ISC capable of handling various sensor types up to 12 bits. This chip transmits optimized images over Ethernet to the SAMA7D65.
The SAMA7D65 is an Arm Cortex-A7 application processor running Linux, which receives the video stream through a 100/1000 Ethernet MAC with TSN support. The system was tested on the SAMA7D65 Curiosity Kit, which includes storage options like microSD and various flash types. Additional features of the kit include dual Ethernet ports and security support via a physically unclonable function (PUF) for secure boot and crypto acceleration.
Full Take
The architecture illustrates a clear functional split: one processor manages the high-throughput sensory input and image preparation (SAM9x75), while the other executes the computationally intensive application logic (SAMA7D65). This modular design, utilizing dedicated components like the ISC and Ethernet for data transfer, suggests an approach to offloading specialized tasks in embedded AI systems. The focus on specific interfaces (MIPI CSI-2) and networking protocols (Ethernet/TSN) highlights a pathway for integrating sophisticated processing into standard smart home infrastructure.
The underlying implication is that achieving real-time, distributed facial recognition requires careful partitioning of workloads across heterogeneous processors. The inclusion of security features like PUF in the hardware layer indicates an awareness that data integrity must be addressed at the physical level, which shifts security from a purely software concern to a hardware constraint. The pattern observed here involves creating specific hardware interfaces and software stacks tailored for efficiency. A key question arises regarding the scaling—how effectively this split minimizes latency while maximizing the utilization of the specified memory and I/O bandwidths in real-world, dynamic smart home scenarios. What external factors, such as power constraints or thermal management, are implicitly assumed to be managed by these specific processor selections?
Sentinel — Human
The text reads like a human-authored technical summary or press release based on specific expert interviews, providing detailed specifications and context for an embedded AI application.