Tesla's AI5 with 2nm-class node tapes out at Samsung Foundry — production starts soon, months after TSMC tape out

Several months after tape out at TSMC.
Tesla's AI5 chip is about to enter mass production at Samsung Foundry using the company's 2nm-class process technology, a principal engineer at Samsung Foundry disclosed in a LinkedIn post, as noticed by Sawyer Merritt. As it turns out, the chip has been taped out recently.
"The Tesla-Samsung Al5 chip has reached tape-out," James Kim, a principal engineer at Samsung Foundry, wrote in the LinkedIn post. "It is scheduled to be manufactured at the Taylor fab using our latest 2nm process and will soon be integrated into Tesla's newest products. It has been an honor to collaborate with the outstanding engineers at Tesla Palo Alto and Austin over the past several months."
Elon Musk demonstrated the first sample of Tesla's AI5 in mid-April and revealed that the processor will be concurrently made both at TSMC and Samsung Foundry. Apparently, AI5 implemented in a TSMC process technology reached taped out several months ahead of AI5 implemented using a Samsung Foundry.
Tesla’s AI5 processor module that Elon Musk demonstrated in April integrates a relatively compact accelerator die — roughly half a reticle in size, based on Musk's earlier remarks — alongside 12 SK hynix memory packages that appear to be standard GDDR6 or GDDR7 devices. The package relies on an organic substrate, and the memory components are labeled similarly to conventional discrete DRAM chips.
Tesla has not revealed the width of AI5's memory subsystem, but the presence of 12 memory packages points to a relatively broad external memory interface. Assuming the module indeed uses 12 GDDR6 or GDDR7 ICs, the processor would feature a 384-bit memory bus. Depending on the memory technology and transfer rates employed, this would translate into memory bandwidth ranging from 768 GB/s all the way to 1.536 TB/s.
The company has not disclosed AI5's peak compute performance, or other detailed performance specifications, but Musk has previously claimed that, in certain workloads, AI5 can deliver performance improvements of up to 40X compared to its predecessor.
Musk expects AI5 to be one of the most produced chip ever, which is why Tesla plans to use two foundries to make it. AI5 is projected to be used in Tesla cars, Tesla robots, and in Tesla's data centers.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

Facts Only

* The Tesla-Samsung AI5 chip has reached tape-out.
* It is scheduled to be manufactured at Samsung Foundry using a 2nm-class process technology.
* The tape-out occurred several months after the tape-out at TSMC.
* James Kim, a principal engineer at Samsung Foundry, stated the AI5 chip reached tape-out.
* Manufacturing is scheduled at the Taylor fab using the latest 2nm process.
* Elon Musk demonstrated the first sample of the AI5 in mid-April.
* The processor will be concurrently made at TSMC and Samsung Foundry.
* The module integrates a compact accelerator die and twelve SK hynix memory packages.
* The memory components appear to be standard GDDR6 or GDDR7 devices.
* If the module uses 12 GDDR6/GDDR7 ICs, it would feature a 384-bit memory bus.
* Memory bandwidth is projected between 768 GB/s and 1.536 TB/s.
* Musk claimed AI5 can deliver performance improvements of up to 40X in certain workloads.
* AI5 is projected for use in Tesla cars, robots, and data centers.

Executive Summary

Tesla's AI5 chip has reached tape-out, and production is scheduled to commence soon at Samsung Foundry utilizing its 2nm-class process technology. A principal engineer at Samsung Foundry confirmed that the Tesla-Samsung AI5 chip will be manufactured in the Taylor fab using this process and integrated into Tesla's new products. Elon Musk previously demonstrated a sample of the AI5 in mid-April, revealing plans for concurrent manufacturing at both TSMC and Samsung Foundry. The module integrates a compact accelerator die and twelve SK hynix memory packages, likely GDDR6 or GDDR7 devices, suggesting a memory bus capacity potentially ranging from 768 GB/s to 1.536 TB/s depending on the technology used. While peak compute performance remains undisclosed, Musk has previously claimed potential performance improvements up to 40X over predecessors, with expectations that AI5 will be one of the most produced chips. The module is projected for use in Tesla vehicles, robots, and data centers.

Full Take

The narrative juxtaposes the timeline discrepancy between TSMC tape-out and Samsung Foundry's tape-out with the upcoming production phase at Samsung. This juxtaposition highlights a pattern where technological advancements are rapidly distributed across competing fabrication ecosystems to maximize market positioning and potential supply chains, rather than being constrained by a single foundry’s progression. The emphasis on dual-foundry strategy implies an acceptance of operational complexity as a necessary cost for maximizing output, suggesting that speed of deployment in high-demand areas supersedes process fidelity synchronization. Furthermore, the performance claims are presented without concrete benchmarks, relying instead on aspirational projection (40X improvement), which serves to establish perceived revolutionary potential while maintaining strategic secrecy regarding actual capabilities. The implications suggest that competitive advantage in advanced compute relies less on the singular superiority of a node and more on the agility to leverage disparate, cutting-edge manufacturing resources simultaneously. If this pattern continues, the focus shifts from mastering a single technological roadmap to mastering an integrated, multi-source production architecture.