SAN JOSE, Calif. â AI chip startup Etched has raised $300 million in a Series C round at a $10 billion pre-money valuation, bringing the total raised to $1.1 billion. Etchedâs round was led by Sequoia with participation from A16Z, Jane Street, SK Hynix, Diffusion Capital, plus existing investors.
The company already has $1 billion in pre-orders, Etched president Robert Wachen told EE Times on a recent visit to the companyâs San Jose headquarters.
âIn general, we are focused on the biggest AI companies and the biggest AI clusters in the world,â Wachen said. âOur customers are buying many billions of dollars of hardware⦠we expect that the product will be very good for coding, long context, long horizon agents, and a lot of things that inference tokens are going to be used for.â
Customers are already running their workloads remotely in Etchedâs data center with results that are âsignificantly better than anything on the marketâ, Wachen said.
In addition to the cluster and lab up and running in the companyâs San Jose office, Etched recently opened a new R&D facility in Milpitas, Calif., which includes a 10 MW data center plus a lab and quick turn SMT line.
Workload flexibility
Etched, started by Harvard dropouts Gavin Uberti and Chris Zhu with Harvard graduate Robert Wachen, attracted attention two years ago when it said it could beat Nvidia Blackwell-based systemsâ token throughput by an order of magnitude using chips that âburned the transformer architecture into hardwareâ. Today, the technical story has evolved a bit, Wachen said, but the companyâs aims are just as ambitious.
âEarly on, we tried a bunch of different ideas, some very radical, like hard-coding a specific model or a specific model architecture into hardware,â he said. âWhat we realized is that the world needs a new computing paradigm that enables more FLOPS and bandwidth, that can run any type of inference workload, whether thatâs multi-trillion parameter MoE models, or diffusion, or state-space models.â
More flexibility on workloads is part of Etchedâs technical evolution, along with a broader focus on system and cluster-level topologies, in keeping with industry trends, Wachen said.
EE Times visited the Etched office in San Jose for a tour of the lab and an impressive large MoE inference demo, and was able to see racks of hardware up and running in prefill and decode configurations. Etched declined to make performance figures public at this stage, however.
Vertical integration
The company is vertically integrated, since its ambitious design has meant taking on parts of the stack other fabless startups usually wouldnât. Every part of Etchedâs rack, from the ASIC design to custom packaging, board design and cooling to server and infrastructure design, was done in-house, Wachen said.
âWeâre deep believers in vertical integration,â he said. âItâs not enough to build a chip, itâs not enough to build the server, itâs not enough to build the rack, itâs not even enough to build a cluster. You have to build a machine that can produce the best clusters in the world at gigawatt scale.â
Etched is both dogmatic and pragmatic about its vertically integrated approach, Wachen said. The overall aim is simply to do what it takes to serve more tokens than the competition. Itâs a big ask for a startup, but the team is over 450 and growing.
Low-voltage inference
A big part of Etchedâs performance comes from utilization, which indirectly comes from turning down the voltage for parts of its chips. Todayâs big AI chips suffer from thermal issues, which means cores have to be throttled (clock frequency reduced to reduce heat loss), with a resulting loss in performance.
Etched is running the transistors in its math engines at âunder halfâ the voltage other AI chips use in a scheme it calls low-voltage inference (LVI). This enables more FLOPS per Watt, and it also means better utilization of those FLOPS, Wachen said, since throttling isnât required. The company can run at 80%+ utilization for trillion-parameter MoE models without thermal throttling.
âThe current state of affairs is that for every FLOPS I buy, Iâm really getting 0.2 to 0.4 FLOPS,â he said. âIf every chip in the world ran LVI, we could double or triple the worldâs inference capacity.â
There is a reason sub-threshold designs are generally limited to small chips (such as Ambiqâs microcontrollers) and crypto-mining ASICs. Running at low voltage means extremely high current, with resulting challenges in handling current spikes, and in general the clock frequencies that can be achieved are very slow.
âThis is an extremely hard physical problem,â Wachen said. âThere’s tons of innovations across the stack from things at the fabrication level, things at the ASIC design, packaging, board, cooling and mechanical levels. Everything has to go together to make this happen.â
Will Etched have to reduce its clock frequency significantly to make it all work?
âNot necessarily,â Wachen said. âOf course, itâs hard to run a high clock speed at low voltage, mainly because the current goes up, but there are ways to solve these problems. One of the breakthroughs is how to run at much lower voltages than GPUs or other AI chips while being able to run a much larger amount of silicon.â
Part of the solution is running only the math engines at lower voltage; the chipâs SRAM blocks canât (sub-threshold operation isnât possible today for standard SRAM cells as it reduces the stability too much). For this reason, competitorsâ designs that finely mix compute and SRAM would find low-voltage operation harder, Wachen said.
âThese are hard problems to be solved, but our hardware is the proof weâve found a solution,â he said.
Etchedâs chip is on TSMC N4P, and itâs a full-reticle-sized design with six stacks of HBM. Wachen said the chip deliberately uses a different process node, different packaging technology, and different memory than Nvidiaâs next-generation Rubin GPUs to enable both to get to scale simultaneously.
Cluster-scale memory
Another of Etchedâs key innovations is a low-latency shared memory pool across a whole cluster in a single scale-up domain using a custom high-bandwidth interconnect for fast access to both SRAM and HBM across chips.
âThat meant both a new type of interconnect and a new type of memory subsystem had to be co-designed throughout the stack to make it possible,â Wachen said. âAnd we need to do that with technologies that exist and are mass-producible today, including copper.â
In Etchedâs lab, the company has split prefill and decode stages across separate racks of Etched chips, and can easily handle both because of their compute and bandwidth, Wachen said. That said, Etched would be just as happy to be deployed alongside other hardware in a disaggregated setup, he added.
Etched racks will start shipping to customers this summer.
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Facts Only
* Etched raised $300 million in a Series C round at a $10 billion pre-money valuation, totaling $1.1 billion raised.
* The funding round was led by Sequoia with participation from A16Z, Jane Street, SK Hynix, and Diffusion Capital.
* The company has $1 billion in pre-orders.
* Customers run workloads remotely in Etched's data center with better results than the market.
* Etched focuses on the biggest AI companies and clusters in the world for hardware solutions.
* The company developed chips that burn the transformer architecture into hardware.
* Etched runs math engines at under half the voltage of other AI chips in a scheme called low-voltage inference (LVI).
* This LVI enables higher FLOPS per Watt and utilization up to 80%+ for trillion-parameter MoE models without thermal throttling.
* The chip is on TSMC N4P and uses a different process node, packaging, and memory than Nvidia's Rubin GPUs.
* Etched implemented a low-latency shared memory pool across a cluster using a custom high-bandwidth interconnect.
* A new R&D facility, including a 10 MW data center, was opened in Milpitas, California.
Executive Summary
Etched recently secured $300 million in a Series C round, valuing the company at a $10 billion pre-money valuation, bringing total raised to $1.1 billion. The funding round was led by Sequoia with participation from A16Z, Jane Street, SK Hynix, and Diffusion Capital. The company focuses on optimizing AI hardware for large AI companies and clusters worldwide, aiming to improve performance for coding, long context agents, and inference token usage. Customers are currently running workloads remotely in Etched's data center, reporting performance superior to current market offerings.
The company’s technical approach involves developing chips that burn the transformer architecture into hardware, seeking to achieve higher FLOPS and bandwidth than existing systems. A key innovation is low-voltage inference (LVI), where transistors operate at under half the voltage used by other AI chips, which improves performance per watt and utilization by avoiding thermal throttling. Etched has pursued vertical integration, designing every component in-house, from ASIC design to packaging and cooling. They also developed a novel cluster-scale memory pool using a custom interconnect for low-latency access across a cluster. Furthermore, the company has expanded its physical footprint by opening a new R&D facility in Milpitas, California.
Full Take
The narrative presents a tension between radical technical achievement and the pragmatic realities of scaling hardware. Etched's ambition to redefine AI computing by integrating the entire stack—from ASIC design through cluster topology—reflects a deep-seated conviction in vertical integration. The shift toward low-voltage inference (LVI) is not merely an optimization; it suggests a fundamental rethinking of the physical constraints of computation, challenging the established thermal and clock frequency paradigms in the AI hardware space. The success in achieving high utilization without throttling implies that the bottleneck shifts from raw clock speed to managing current flow and utilizing energy more efficiently across the entire system architecture.
The pattern here is one of iterative technological evolution driven by necessity: realizing that building individual components is insufficient; true advancement requires co-design at every layer, from silicon to cluster memory. The implication for the broader industry is that future scaling of AI capacity may depend less on incremental clock speed increases and more on solving the physics of energy efficiency and holistic system integration simultaneously. However, this pursuit necessarily involves navigating immense physical challenges, as evidenced by the difficulty in achieving sub-threshold operation and managing current spikes. The focus on LVI and cluster memory co-design suggests a necessary move toward systemic innovation rather than isolated component breakthroughs.
What limitations are implicit in claiming that existing technologies (like copper interconnects) can solve "extremely hard physical problems"? Does the momentum of the funding round mask the potential for significant unforeseen engineering roadblocks in mass production? How does the focus on being "dogmatic and pragmatic" balance the inherent risk associated with pushing physics at the extreme limits, particularly concerning long-term supply chain viability versus immediate performance gains?
Sentinel — Human
The text reads like a feature interview or detailed industry report, characterized by an embedded personal perspective alongside factual data, suggesting a human journalistic origin.