* Researchers from the University of Lübeck published a technical paper.
* The paper is titled “SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.”
* SPARC is an automated framework for pre-silicon PSCL evaluation and root-cause analysis.
* SPARC leverages macro-cell-level Information Flow Tracking (IFT).
* The framework uses enhanced shadow logic to tag switching activity originating from secret-dependent data.
* SPARC applies statistical leakage tests to detect Power Side-Channel Leakage (PSCL) by isolating the tagged activity.
* SPARC attributes the detected leakage to specific hardware signals.
* The hardware signals are mapped to corresponding software instructions.
* The work was presented at ICCAD ’26 in San Jose, CA, USA, in November 2026.

Researchers from the University of Lübeck developed SPARC, an automated framework designed for evaluating and performing root-cause analysis on pre-silicon power side-channel leakage within the processor design flow. The framework utilizes macro-cell-level Information Flow Tracking (IFT) combined with enhanced shadow logic to identify switching activity derived from secret-dependent data. SPARC then uses this isolated activity to apply statistical leakage tests for detection and attribute the resulting leakage to specific hardware signals, subsequently mapping those signals back to corresponding software instructions.
The work was presented at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’26) in San Jose, CA, USA, in November 2026. The publication details the development of SPARC as an automated method for analyzing power side-channel leakage during the pre-silicon stage of processor design.

The development of SPARC exemplifies a trend toward automating complex security analysis within the semiconductor design flow, moving from manual, post-silicon verification to integrated, pre-silicon assurance. The core implication lies in bridging the gap between abstract software execution and concrete physical leakage measurements by formally linking information flow (IFT) directly to physical phenomena (switching activity). This methodology suggests that attributing side-channel leakage to specific instruction execution provides a tangible path for designing hardware defenses tailored to the data dependency itself, rather than broad power consumption constraints.
The pattern observed is a move toward holistic analysis where theoretical security boundaries are operationalized through algorithmic tracking. The inherent value of this approach rests on whether the complexity of the tracking and attribution mechanism can be scaled efficiently across increasingly large and complex processor designs without introducing new blind spots or excessive computational overhead during the design phase. The challenge shifts from *detecting* leakage to establishing verifiable, traceable causality between software logic and physical manifestation in a way that is robust against adversarial manipulation within the design flow itself.
What further study is needed to establish the robustness of the attribution model across diverse logic families? How does the IFT mechanism handle data-dependent branching or speculative execution paths that are common in modern processor architectures? Does this framework generalize beyond static instruction mapping to dynamic, runtime leakage prediction during simulation?