Major memory deal; AI Infra Summit news; U.S. chip capacity plans; 2nm & below advances; Huawei’s chip offensive; RoT solution for data centers and AI SoCs; Chinese equipment makers gain share; India’s chip build-out; McKinsey’s tech trends; major funding rounds; Europe’s AI infrastructure gaps.
Memory
- Infineon agreed to sell its NOR flash and F-RAM businesses to Winbond for $1.12B in cash, allowing it to concentrate resources on its core semiconductor businesses. The deal is expected to close in the second half of 2027.
- SK hynix is reportedly in exploratory talks with Intel to manufacture memory chips in the U.S., potentially by leasing part of Intel’s Ohio fab or forming a joint venture with Intel and cloud providers. SK hynix said no plans or agreements have been finalized.
- Micron Technology debuted a 512GB DDR5 module for servers that vertically stacks DRAM dies interconnected by TSVs.
- Deirdre Hanford will lead Micron Research Labs.
Huawei’s AI chip offensive
- Huawei unveiled an 11-chip AI portfolio spanning compute, interconnect, and storage. The company said its Ascend 960 processors will double the compute performance of the 950 series, with two variants arriving ahead of schedule in 2027. Huawei is relying on system-level scaling to help offset limitations in individual chip performance.
Advanced nodes
- CSIS said the cost of designing a leading-edge 2nm chip has climbed to about $725M, up from $48M at 28nm, putting advanced chip development beyond the reach of most companies. It contends that U.S. semiconductor policy needs to address rising design costs and manufacturing capacity, especially as China invests heavily in developing its own chips.
- MediaTek launched its first 2nm smartphone processor, the Dimensity 9600 Pro, with an upgraded NPU for generative AI.
- Sub-2nm manufacturing is blurring traditional process boundaries as shrinking dimensions and tighter margins make test, metrology, inspection, and manufacturing increasingly interdependent.
North America capacity
India’s build-out
- Applied Materials announced a $5B investment plan for India through 2035, including a new 140-acre semiconductor research park, a tenfold expansion of its India-based supply-chain capacity, and expanded R&D and workforce development.
- Fujifilm will invest approximately $83 million in a semiconductor materials plant in Dholera, Gujarat, to supply Tata’s upcoming fab and support local production of high-purity chemicals.
- Tata Electronics partnered with Besi to develop advanced packaging capabilities at Tata’s semiconductor packaging facility in Assam.
Analysis
- Chinese semiconductor equipment makers gained global market share in 2025, particularly in ion implantation, deposition, and etch and cleaning tools, reports CSET. China’s share reached 12.6% in CMP, 10.2% in etch and cleaning, and 9.8% in deposition. Lithography remains a weakness, and Chinese suppliers lost share in assembly, test, and packaging equipment.
- Omdia reports global semiconductor revenue jumped 31.4% sequentially to a record $425B in Q2 2026, driven by AI demand and rising memory prices. The firm expects Q3 revenue to top $500B.
- McKinsey’s 2026 Technology Trends Outlook highlights growing demand for AI chips that are optimized for inference workloads. Amazon, Google, Meta, and Microsoft are co-designing custom silicon with semiconductor companies and considering commercial sales of those chips.
Funding frenzy
- Enflame, developer of AI training and inferencing chips, listed on Shanghai’s STAR Market, raised ~$912M.
- Fortaegis raised $50M to commercialize its full-stack secure compute architecture.
- Polaris Electro-Optics raised $50M to produce electro-optic modulators.
- TeRAM emerged from stealth with $37M to develop memory and packaging technologies to integrate 3D SRAM directly onto AI compute chips.
- Euclyd raised over ~$231M to build agentic AI silicon that combines programmable ASIC compute, processor-memory co-design, and system-level optimization.
Around the Valley
News from this week’s AI Infra Summit in Santa Clara:
- Cornelis introduced an open architecture spanning scale-up and scale-out networking with programmable compute built into the fabric. The company also announced $205M in funding and a collaboration deal with Qualcomm.
- Delos Data unveiled its nonstop AI data interface and raised over $100M. Its architecture targets latency and data movement between different types of AI accelerators.
- Astera Labs debuted new memory connectivity solutions for direct fabric-attached GPU memory, CPU-attached expansion, and pooled/shared memory architectures.
- Credo introduced 1.6T ZeroFlap optical transceivers using 224G-per-lane technology.
- Arteris unveiled a multi-die product that extends NoC connectivity and data movement transparently across die-to-die links for non-coherent AI and HPC architectures, with support for virtual channel link technology and advanced QoS mechanisms.
- SignatureIP introduced a mesochronous connectivity bridge IP core that lets PCIe/CXL designs run at their native speed and lane width during emulation and prototyping.
Fig. 1: A mix of infrastructure, physical and edge AI, servers, and tools at AI Infra Summit.
Quick links to more news:
In-Depth
Reports and Deals
New Technologies
Security
Vehicles, Batteries
Trending Video
Research
Quantum
Workforce | Education
Events and Webinars
Global
Asia
Europe
- The Global Electronics Association and DECISION Études & Conseil issued a report that showed EU-headquartered companies capture just 6% of the EU market for data-center semiconductors, 7% for server manufacturing and assembly, and 8% for cloud infrastructure. Since 2021, EU demand for server systems has grown 36% annually, compared with 20% for domestic manufacturing, highlighting gaps in Europe’s AI infrastructure supply chain.
Reports and Deals
More deals, launches
More fundings
Reports and opinions
TrendForce reports:
- NOR flash supply is expected to remain tight through the rest of the year, with potential price increases of 90% to 110% for high-capacity products;
- Combined revenue of the 10 largest fabless IC design companies increased 73% YoY in 2Q26 to more than $141B;
- Global data center power demand capacity is expected to increase 31% YoY to reach 161 GW in 2026.
And:
New Technologies
Power
- Infineon introduced a 120 V dual-channel gate driver for high-density AI data center power systems, with a compact 2.2 × 2.2 mm package, independent MOSFET control, and thermal management capabilities to support higher server rack density.
- Onsemi introduced an embedded power platform that uses the silicon wafer as the foundation of the package. The approach integrates silicon, SiC, and GaN in a wafer-level architecture that embeds FETs, drivers, and controllers in a single package for power-system co-design.
AI computing and chip design
- Axelera AI announced an AI processing unit targeted at enterprises running a mix of persistent AI inference workloads.
- Ambarella launched a standalone edge AI accelerator that brings physical AI capabilities to already-deployed Arm and x86 host processors.
- Cognichip launched a full-stack AI design system that uses physics-informed foundation models to perform chip design tasks, including completing the micro-architecture, RTL design, functional verification, and PPA optimization.
Connectivity and interfaces
Research
NUS-led researchers developed a reconfigurable transistor using atomically thin MoS₂ and ferroelectric HZO that can operate as a logic device, artificial synapse, or artificial neuron, allowing a single device to support different computing functions.
USC is leading a $5.5M DARPA-funded project to develop a transistor that processes information using magnetic spin waves, instead of electrical charge, aiming to reduce computing power consumption and heat and to be compatible with conventional chip manufacturing.
More academic papers
Security
New tools
- Rambus introduced a CryptoManager Root of Trust supporting the Caliptra specification for data center and AI SoCs, with PQC and protection against side-channel and fault-injection attacks.
Alerts and vulnerabilities
- KU Leuven and other researchers disclosed DDRop, a low-cost DDR5 interposer attack that silently drops memory writes and can compromise confidential virtual machines. It requires physical installation and privileged software access. AMD says the attack falls outside its SEV-SNP threat model and does not plan a mitigation.
- Microchip disclosed a physical side-channel vulnerability affecting cryptographic libraries and application-note implementations that could expose encryption keys.
- Google DeepMind researchers found that competitive multi-agent AI systems can spread cheating behavior through shared communications, while also using those same channels to detect, report, and counter misconduct.
Government updates
Security technical papers
Vehicles, Batteries
Automotive chips and standards
AVs and drones
EVs and batteries
- VTT, Fraunhofer, and others developed a cloud-based digital-twin architecture for battery management systems that keeps real-time monitoring at the edge while shifting more computationally intensive health estimation and prognostics to the cloud.
- Volkswagen’s aerodynamic Mission Efficiency EV prototype traveled ~794 miles with one recharge and finished with ~102 miles of range remaining. Its solar roof and rear-window panels can add up to 19 miles of range per day under favorable conditions.
Fig. 2: Volkswagen AG’s Mission Efficiency EV prototype
Vehicle technical papers
Trending Video
Smart Outlier Detection: Just because a chip is deemed good doesn’t mean it will work as expected. Nir Sever, senior director of business development at proteanTecs, explains how to train machine learning models to identify outliers in context, replacing a rigid pass/fail decision tied to a spec with one that assesses its usefulness based on its behavior under real workloads in a complex system.
Quantum
The U.S. Department of Energy launched a competition with up to $215M for quantum computers with at least 100 logical qubits that are capable of performing hundreds of millions of fault-tolerant operations and scientific demonstration programs.
Quobly demonstrated key quantum operations on a quantum chip fabricated by STMicroelectronics that combines silicon spin qubits with FD-SOI transistors.
Nvidia extended its CUDA-Q platform with an orchestration layer for developing fault-tolerant quantum computing applications.
Quantum technical paper: Spacetime mitigation of logical errors (IBM)
Workforce, Education
A federal judge temporarily blocked a DHS rule that would have replaced “duration of status” for F-1 students and J-1 exchange visitors with fixed admission periods of up to four years. The ruling keeps current rules in place for now, including existing OPT and STEM OPT pathways used by semiconductor employers.
The U.S. Department of Energy launched a $16M workforce-training prize for universities to develop programs in critical minerals production and processing.
Upcoming semiconductor career fairs and recruiting events:
Events and Webinars
Upcoming webinars are here, including:
Find upcoming chip industry events here, including:
| EVENTS |
Date |
Location |
| GSA: 2026 U.S. Executive Forum |
Sept. 22 |
Menlo Park, CA |
| TSMC 2026 North America OIP Ecosystem Forum |
Sept. 23 |
Santa Clara, CA |
| Keysight Design Forum 2026 |
Sept. 24 |
Santa Clara, CA |
| IMAPS Symposium 2026 |
Sept. 28–Oct. 1 |
Boston, MA |
| Microelectronics UK |
Sept. 29–30 |
London, UK |
| IEEE International 3D Systems Integration Conference (3DIC) |
Oct. 1–2 |
Atlanta, GA |
| International Test Conference |
Oct. 11–16 |
San Antonio, TX |
| 2026 OCP Global Summit |
Oct. 12–15 |
San Jose, CA |
| SEMICON West 2026 |
Oct. 13–15 |
San Francisco, CA |
| Cadence Connect: Celebrating the Photonics Journey from Flicker to Brilliance |
Oct. 14–15 |
San Jose, CA |
| PDF Solutions CONNECT: For Semiconductor Manufacturing Analytics and AI |
Oct. 15–16 |
San Francisco, CA |
| 2026 EPEPS Conference: Electrical Performance of Electronics Packaging and Systems |
Oct. 18–21 |
Fort Worth, TX |
| Synaptics Tech Day 2026 |
Oct. 20 |
San Jose, CA |
| Jasper User Group 2026: Cadence Connect |
Oct. 21–22 |
San Jose, CA |
| OktoberTech Silicon Valley |
Oct. 22 |
Mountain View, CA |
| CASPA 35th Annual Conference and Dinner Banquet |
Oct. 23–24 |
Santa Clara, CA |
| IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) |
Oct. 27–29 |
Phoenix, AZ |
| Micro 2026: IEEE/ACM International Symposium on Microarchitecture |
Oct. 31–Nov. 4 |
Athens, Greece |
Find all events here.
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Facts Only
* Infineon agreed to sell NOR flash and F-RAM businesses to Winbond for $1.12B cash.
* SK hynix is in exploratory talks with Intel regarding memory chip manufacturing in the U.S.
* Micron Technology debuted a 512GB DDR5 module using vertically stacked DRAM dies interconnected by TSVs.
* Huawei unveiled an 11-chip AI portfolio, including Ascend 960 processors, with performance targets set for 2027.
* The cost of designing a leading-edge 2nm chip reached approximately $725M, up from $48M at 28nm.
* MediaTek launched the Dimensity 9600 Pro smartphone processor with an upgraded NPU for generative AI.
* Applied Materials announced a $5B investment plan for India through 2035, including a semiconductor research park.
* Fujifilm will invest approximately $83 million in a semiconductor materials plant in Dholera, Gujarat.
* Chinese equipment makers gained global market share in ion implantation, deposition, etch and cleaning tools in 2025.
* Global semiconductor revenue reached $425B in Q2 2026, driven by AI demand and rising memory prices.
Executive Summary
Full Take
The narrative reveals a dynamic tension between aggressive technological advancement and the vast capital requirements needed to sustain it, particularly concerning advanced nodes like 2nm. The escalating design costs suggest a structural bottleneck where policy interventions in capacity and design access are becoming as critical as purely technological breakthroughs. The focus on AI infrastructure signals a fundamental shift towards system-level co-design, evidenced by companies co-designing custom silicon and the emergence of novel memory integration techniques like stacking DRAM dies via TSVs.
The pattern observed is a convergence where physical constraints (design costs, manufacturing capacity) dictate strategic action, while market competition (Chinese equipment makers gaining share) forces operational realignments. The funding frenzy around agentic AI silicon and memory packaging suggests that the immediate path forward involves integrating disparate functions—compute, memory, and interconnect—onto cohesive silicon substrates. This implies that future competitive advantage will not solely reside in raw transistor density but in the efficiency of system-level integration and the ability to manage complex, multi-die architectures securely and with low latency. The implication is that geopolitical competition around chip dominance will increasingly manifest through control over the entire supply chain stack, from materials science to advanced packaging and AI application layers.
What assumptions are embedded here about the sustainability of current economic models if design costs continue to rise exponentially? How does the reported division of market share—where established players face intense pressure while new entrants capture specific tool markets—reflect a broader trend in how technological supremacy is defined? What are the long-term consequences for geographic distribution of high-value manufacturing capacity given India's and Europe's stated infrastructure gaps?
Sentinel — Human
This text appears to be a synthesized compilation of recent semiconductor and AI industry news, characterized by the integration of specific financial data, technological advancements, and geopolitical context.